In the past, the xe2x80x9cboard test coveragexe2x80x9d provided by a particular test suite was often measured in terms of xe2x80x9cdevice coveragexe2x80x9d and xe2x80x9cshorts coveragexe2x80x9d. Device coverage was measured as the percentage of board devices with working tests, and shorts coverage was measured as the percentage of accessible board nodes.                               Device          ⁢                      xe2x80x83                    ⁢          Coverage                =                              #            ⁢                          xe2x80x83                        ⁢            Tested            ⁢                          xe2x80x83                        ⁢            Devices                                Total            ⁢                          xe2x80x83                        ⁢            #            ⁢                          xe2x80x83                        ⁢            of            ⁢                          xe2x80x83                        ⁢            Devices                                                            Shorts          ⁢                      xe2x80x83                    ⁢          Coverage                =                              #            ⁢                          xe2x80x83                        ⁢            Accessible            ⁢                          xe2x80x83                        ⁢            Nodes                                Total            ⁢                          xe2x80x83                        ⁢            #            ⁢                          xe2x80x83                        ⁢            of            ⁢                          xe2x80x83                        ⁢            Nodes                              
The above model of board test coverage was developed at a time when testers had full nodal access to a board (i.e., access to the majority (typically 95-100%) of a board""s nodes). Boards were also less dense, less complex, and somewhat more forgiving due to their lower frequency of operation. In this environment, the above model was acceptable.
Over the last decade, boards have migrated towards limited access. In fact, it is anticipated that boards with access to less than 20% of their nodes will soon be common. Some drivers of access limitation include:
Increasing board density (devices/square centimeter is increasing)
Fine line and space geometry in board layouts (i.e., smaller probe targets)
Grid array devices of increasing pitch density
High-frequency signals that demand precise layouts and offer no probe targets
Board node counts that are several times greater than the maximum available on any tester
The above changes have made application of the xe2x80x9coldxe2x80x9d model of board test coverage difficult at best, and meaningless in many cases.
Usefulness of the xe2x80x9coldxe2x80x9d model of board test coverage has also been impacted by the advent of new and radically different approaches to testing (e.g., Automated Optical Inspection (AOI) and Automated X-ray Inspection (AXI)). Many of the new test approaches are very good at testing for certain defects, but limited in terms of the number of defects they can test. Thus, more and more often, it is becoming erroneous to presume that a device with working tests is a sufficiently tested device. As a result, a board is often submitted to different test processes, which in combination define the xe2x80x9ctest suitexe2x80x9d for a particular board (see FIG. 2).
Given the above state of characterizing board test coverage, new methods and apparatus for characterizing board test coverage are needed.
According to one exemplary embodiment of the invention, a method for characterizing board test coverage commences with the enumeration of potentially defective properties for a board, without regard for how the potentially defective properties might be tested. For each potentially defective property enumerated, a property score is generated. Each property score is indicative of whether a test suite tests for a potentially defective property. Property scores are then combined in accordance with a weighting structure to characterize board test coverage for the test suite.